The embedded system for specified application or applications is in widespread use. The embedded system is applied in a diversity of fields, such as household electrical devices or automobiles. In the embedded system, the number of subjects controlled by a sole processor is increasing and, in keeping up therewith, the number of interrupt signals handled by the processor is also increasing. In case the processor performs system control of the electronic control equipment, at the same time as it performs self-diagnosis of the system and data backup, for example, the processor is supplied with interrupts relevant to system control and with interrupts relevant to self-diagnosis of the system and data backup.
In the system control of the electronic control equipment, the processor deals with interrupts, produced from time to time, in a manner consistent with incessantly changing operating statuses of the electronic control equipment. If the time as from the time of occurrence of an interrupt relevant to system control until actual termination of the processing exceeds a preset period of time (time constraint), the system control cannot catch up with the rate (speed) of changes in the status of the electronic control equipment, thus leading to hindrances in the system control. For this reason, the processor is required to terminate the relevant processing within a preset period of time as from the occurrence of the interrupt and to return the result. That is, a high real-time performance is required of the processor. The real-time performance herein means, in general, the capability of the system in satisfying the time constraint imposed thereon. On the other hand, as to the self-diagnosis of the system and data backup, no serious problems are raised even if the period of time as from the time of occurrence of the interrupt until the actual termination of the relevant processing is varied from time to time, such that no high real-time performance is required.
In the above processor, the time constraint, imposed on the processor, is varied with the operating states of the electronic control equipment, such that, if the electronic control equipment is high in its operating speed, the time constraint imposed on the system control is shorter, whereas, if the electronic control equipment is low in its operating speed, the time constraint imposed on the system control is longer. If the time constraint, imposed on the system, is short, or if the processing performed per unit time is increased, the allowance of the processing capability of the processor is decreased, so that, if the processor is capable of accepting the totality of the interrupts and, in this condition, excess interrupts have occurred, the processing can occasionally not be completed within the limit period of time and hence the processing may not be executed in time.
Usually, each interrupt occurs on its own factor, in a manner asynchronous with the processor operation, so that, although the occurrence itself of the interrupt cannot be suppressed, it is possible to control the interrupt that is acceptable by the processor. In this interrupt control, if there is only insufficient allowance in the processing capability of the processor, an interrupt controller operates for temporarily masking and reserving the interrupts that are only low in the real-time performance required, such that only the interrupts that are high in the real-time performance required will be accepted by the processor. This technique of temporarily masking the interrupts is disclosed in, e.g., Patent Documents 1 and 2, for example.
FIG. 6 shows a portion of a semiconductor device having the interrupt controller, as described in the Patent Document 2. An interrupt controller 202 includes an interrupt mask table 203. For each of input plural interrupt signals, the information as to whether or not these interrupt signals are to be masked, respectively, is written in the interrupt mask table 203. The interrupt mask table 203 is configured for being rewritable depending on the processing state of the CPU 201. For each interrupt signal, a priority rank is set, in dependence upon the real-time performance as required. The higher the real-time performance required of an interrupt, the higher is the priority rank accorded to an interrupt in question.
The interrupt controller 202 refers to the interrupt mask table 203 and, if the information to the effect that a given interrupt signal, out of plural input interrupt signals, is to be masked, the interrupt controller masks the interrupt signal and does not transmit the signal to the CPU 201. If conversely the information to the effect that a given interrupt signal, out of plural input interrupt signals, is not to be masked, the interrupt controller does not mask the interrupt signal and transmits the signal to the CPU 201. In this manner, only the desired interrupt signal, for which the information to the effect that the signal is not to be masked is written in the interrupt mask table 203, is rendered acceptable by the CPU 201.
In the embedded system, whether or not there is certain allowance in the processing capability of the CPU 201 is verified by the operating status of the equipment being controlled. Should there be certain allowance in the processing capability of the CPU 201, the information to the effect that no interrupt signals are masked is written in an interrupt mask table 203, so that the totality of the interrupt signals are rendered acceptable by the CPU 201. If conversely there is not certain allowance in the processing capability of the CPU 201, the information to the effect that the interrupt signals with a low priority rank are masked is written in the interrupt mask table 203, such that only the desired interrupt signals with a high priority rank are rendered acceptable by the CPU 201.
FIG. 7 shows interrupt signals, rendered acceptable by the CPU 201, in relation to the progress of the processing. The CPU 201 performs the processing of phases 1 to 6 in chronological sequence. In the present example, there are 16 interrupt signals, entered to the interrupt controller 202, namely the interrupt signals INT(0) to INT(15), there being four priority ranks of PRI#0 to PRI#3. It is noted that the smaller the suffix number, the higher is the rank of priority, such that the ranking is PRI#0>PRI#1>PRI#2>PRI#3.
In the example of FIG. 7, the priority ranks of the interrupt signals INT(0), INT(4), INT(8) and INT(12) are set to the priority rank PRI#0, whilst those of the interrupt signals INT(1), INT(5), INT(9) and INT(13) are set to the priority rank PRI#1. The priority ranks of the interrupt signals INT(2), INT(6), INT(10) and INT(14) are set to the priority rank PRI#2, whilst those of the interrupt signals INT(3), INT(7), INT(11) and INT(15) are set to the priority rank PRI#3.
During the phase 1, the volume of processing is increased, in an apparatus being controlled, such that processing cannot be completed within the constraint period of time, there being no sufficient allowance in the processing capability of the CPU 201. In this state, there are written in the interrupt mask table 203 the information for not masking the INT(0), INT(4), INT(8) and INT(12) and the information for masking the other interrupt signals. This masks all the interrupt signals, set to the priority ranks PRI#1 to PRI#3, such that only the interrupt signals, set in the priority rank PRI#0, are acceptable by the CPU 201.
The phase 2 is such a state in which operating states of the apparatus being controlled are changed, such that the constraint period of time has become slightly longer and some allowance has been produced for the processing capability of the CPU 201. In this state, the information for not masking is also written for the interrupt signals INT(1), INT(5), INT(9) and INT(13), in addition to the interrupt signals for which the information for not masking has been written in the phase 1. This masks the interrupt signals, set to the priority ranks PRI#2 and PRI#3, such that the interrupt signals set in the priority ranks PRI#0 and PRI#1 are acceptable by the CPU 201.
In the phase 3, the allowance of the processing capability of the CPU 201 is of approximately the same level as that of the phase 2, and hence the information written in the interrupt mask table 203 is similar to that for the phase 2, such that the interrupt signals, set in the priority ranks PRI#0 and PRI#1, are acceptable by the CPU 201. In the phase 4, the allowance of the processing capability of the CPU 201 is of approximately the same level as that of the phase 1, and hence the information written in the interrupt mask table 203 is similar to that for the phase 1, such that only the interrupt signals, set in the priority rank PRI#0, are rendered acceptable by the CPU 201.
In the phases 5 and 6, the allowance of the processing capability of the CPU 201 is of the same level as that of the phases 2 and 3, and hence the information written in the interrupt mask table 203 is similar to that for the phases 2 and 3. Thus, in the phases 5 and 6, the interrupt signals, set in the priority ranks PRI#0 and PRI#1, are acceptable by the CPU 203.
[Patent Document 1] JP Patent Kokai Publication JP-A-5-210514
[Patent Document 2] JP Patent Kokai Publication JP-A-8-297581
(FIG. 1 and paragraph 0018)
The disclosure of these Documents 1 and 2 are incorporated herein by reference thereto.